A memory element, also referred to as a storage cell stores one bit. The single bit storage cell has two stable states (logical 0 and logical 1). Typically, a memory element in a Static Random Access Memory (SRAM) includes four transistors that form two cross-coupled inverters with each inverter having a p-channel metal-oxide-semiconductor field-effect transistor (PMOS)-transistor and an n-channel metal-oxide-semiconductor field-effect transistor (NMOS)-transistor. Memory cells made of complementary metal-oxide-semiconductor (CMOS) memory elements are prone to errors such as single event upsets that are also referred to as soft errors. A single event upset occurs when a charged particle causes a transient voltage spike which results in a change of state of the memory element. The charged particle may be due to natural radiation that is present in substrate and die packaging or generated in the substrate by cosmic rays.
A Dual interlocked Storage Cell (DICE) provides protection from soft errors through the addition of redundant transistors to the memory element. The DICE is described in “Upset hardened memory design for submicron CMOS technology” by Calin, T.; Nicolaidis, M.; Velazco, R.; Nuclear Science, IEEE Transactions, Volume 43, Issue 6, Part 1, December 1996 Page(s):2874-2878.
The DICE employs twice the number of transistors as compared to a traditional SRAM storage cell. Instead of the four transistors in a traditional SRAM storage cell, eight transistors form four inverters interlocked together so that the P-transistor and the N-transistor in each inverter are controlled by separate internal nodes. The state (logical 0 or logical 1) of the single bit storage cell is stored by the four inverters as two pairs of complementary values: 1010 or 0101. A stored value of 0101 represents logical 0 and a stored value of 1010 represents logical 1. Each of the internal nodes is connected to a pair of NMOS and PMOS transistors and also controls the operation of another pair of NMOS and PMOS transistors.
After a particle strike on a first internal node, the first internal node transitions to logical 1, if initially logical 0. The first internal node transitions to logical 0, if initially logical 1. After the transient pulse generated by the particle strike disappears, the internal node that controls the operation of the pair of NMOS and PMOS transistors coupled to the first node restores the state of the first node.
However, if a single particle or multiple particles simultaneously strike two or more internal nodes, the DICE may not recover, dependent on which of the internal nodes are struck. The vulnerable combination of internal nodes is dependent upon the stored state of the memory element, due to the asymmetry of the inverters. For example, if the nodes numbered 1-4 store 1010 or 0101 respectively, if nodes 1 and 2 which store different values (10 or 10) are struck, the DICE may recover. However, if nodes 1 and 3 which store the same value (00 or 11) are struck, the DICE will not recover.
Furthermore, although a DICE itself can recover from a single strike, a glitch may appear at the output of the DICE, which in turn may be captured by subsequent DICE, for example, in an SRAM.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.